Thin-film transistors on a flexible substrate

ABSTRACT

A method for is provided forming a thin-film transistor (TFT) on a flexible substrate. The method comprises: supplying a metal foil substrate such as titanium (Ti), Inconel alloy, stainless steel, or Kovar, having a thickness in the range of 10 to 500 microns; depositing and annealing amorphous silicon to form polycrystalline silicon; and, thermally growing a gate insulation film overlying the polycrystalline. The silicon annealing process can be conducted at a temperature greater than 700 degrees C. using a solid-phase crystallization (SPC) annealing process. Thermally growing a gate insulation film includes: forming a polycrystalline silicon layer having a thickness in the range of 10 to 100 nanometers (nm); and, thermally oxidizing the film at temperature in the range of 900 to 1150 degrees for a period of time in the range of 2 to 60 minutes. Alternately, a plasma oxide layer is deposited over a thinner thermally oxidized layer.

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application is a divisional of application Ser. No.10/194,895, filed Jul. 11, 2002, entitled “Thin-Film Transistors Formedon a Metal Foil Substrate,” invented by Voutsas et al.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] This invention generally relates to integrated circuit (IC) andliquid crystal display (LCD fabrication and, more particularly, tothin-film transistors (TFTs) formed on a metal foil substrate and aprocess for forming the same.

[0004] 2. Description of the Related Art

[0005] High quality polycrystalline silicon material is the buildingblock of high performance TFTs that are used in integrated circuits andmicroelectronic devices such as LCDs. The higher the quality of thepoly-Si material, that is, the closer to single-crystal Si material, thebetter the performance of the resultant devices. Therefore, it isdesirable to develop methods that yield high quality polysilicon(poly-Si) material for display or other electronic products.

[0006] The performance of the device is affected not only by thecrystalline quality of the active layer, but also by the quality of thegate insulator film that covers the active layer. Both the bulkproperties of the gate insulator, as well as the properties of theinterface that forms between the gate insulator and the poly-Si layer,are very important for the operation of the device. For Si or poly-Sidevices, the best gate insulator film is SiO2, and the best method offorming a high quality SiO2 film with excellent bulk and interfaceproperties is by thermal oxidation.

[0007] A silicon substrate has a sufficiently high melting point towithstand thermal treatments up to temperatures in the range of 1200° C.Thus, thermal oxidation at 900-1150° C. is possible on silicon wafers.When the substrate, however, is made of glass or plastic, as istypically the case for LCDs and/or flexible/conformable Microsystems,the maximum process temperature window is restricted to much lowertemperatures.

[0008] The use of alternative substrate materials is of interest, as itwould enable the realization of new products that are not otherwisefeasible to make. One particular aspect of interest is flexibility, theability of the microsystem to bend, conform, or maintain its integrityunder external “stress”. These attributes would enable the manufacturingof a variety of one-use products and/or the manufacturing of robustproducts that maintain their functionality under a wide range ofexternal, “environmental” conditions. Therefore, there is motivation todevelop Microsystems, such as displays with electronics, sensors, orother products that combine TFT microelectronic devices, that arerobust, have high performance, and are cheap to make.

[0009] Very high performance transistors can be made on varioussubstrates using laser annealing technology. However, this technique istypically much more expensive than solid-phase-crystallization (SPC).The latter, however, lacks the performance of laser annealing, as theannealing temperatures must be restricted when glass substrates areused.

[0010] It would, therefore, be advantageous if a technology wereavailable that could utilize solid-phase crystallization, but offer theperformance levels of laser annealing in the fabrication of TFTs.

[0011] It would be advantageous if the above-mentioned high-performanceTFTs could be fabricated on a flexible substrate for use in flexibleMicrosystems.

SUMMARY OF THE INVENTION

[0012] The present invention describes a technology that enables thefabrication of high performance devices for flexible microsystemapplications, using a standard, low cost poly-Si TFT process flow. Oneaspect of the invention is the combination of high temperature thermaloxidation with solid-phase-crystallized poly-Si material. Thermaloxidation requires temperatures in the range of 900-1150° C., which isnot compatible with conventional flexible substrates. This problem issolved in the present invention by utilizing flexible thin metal foilsas the starting substrate. Thin metal foils can withstand temperaturesin excess of 1000° C. if certain treatments are applied the initialmetal foil material.

[0013] Accordingly, a method for is provided forming a thin-filmtransistor (TFT) on a flexible substrate. The method comprises:supplying a metal foil substrate such as titanium (Ti), Inconel alloy,stainless steel, or Kovar, having a thickness in the range of 10 to 500microns; depositing amorphous silicon; annealing the amorphous siliconto form polycrystalline silicon; and, thermally growing a gateinsulation film overlying the polycrystalline film.

[0014] The amorphous silicon annealing process can be conducted at atemperature greater than 700 degrees C. using a solid-phasecrystallization (SPC) annealing process. Thermally growing a gateinsulation film includes: forming a first film polycrystalline siliconlayer having a thickness in the range of 10 to 100 nanometers (nm); and,thermally oxidizing the first film layer at temperature in the range of900 to 1150 degrees C. for a period of time in the range of 2 to 60minutes.

[0015] Alternately, thermally growing a gate insulation film furtherincludes plasma depositing a second layer of oxide overlying the firstfilm. Then, the first film has a thickness in the range of 10 to 50 nmand the second layer of oxide overlying the first film has a thicknessin the range of 40 to 100 nm.

[0016] Additional details of the above-described method, and a thin-filmtransistor on a flexible substrate are provided below.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017]FIG. 1 is a partial cross-sectional view of the present inventionthin-film transistor (TFT) on a flexible substrate.

[0018]FIG. 2 is a detailed depiction of the gate insulation oxide filmof FIG. 1.

[0019]FIG. 3 is a flowchart illustrating the present invention methodfor forming a thin-film transistor (TFT) on a flexible substrate.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020]FIG. 1 is a partial cross-sectional view of the present inventionthin-film transistor (TFT) on a flexible substrate. The TFT 100comprises a metal foil substrate 102 with a surface 104. In someaspects, the metal foil substrate 102 is a material such as titanium(Ti), Inconel alloy, stainless steel (304 SS), or Kovar. An electricalisolation layer 106 overlies the metal foil substrate surface. Drain108, source 110, and channel 112 regions are formed from polycrystallinesilicon 113 overlying the electrical isolation layer 106. The TFTfabrication process is a silicon on insulator (SOI) process, in thatactive layer polysilicon islands are formed on an insulation layer. Agate insulation oxide film 114 overlies the polycrystalline siliconhaving an index of refraction in the range of 1.4 to 1.6. A gate 116overlies the gate insulation oxide layer 114.

[0021] A gate insulation oxide layer 114 that can be thermally oxidizedpermits TFT performance enhancements. Thermal oxidation annihilatesstructural defects that would otherwise impede carrier conduction.Further, thermally oxidized, or thermally grown gate insulation materialpermits the threshold voltage of the TFTs to be more accuratelycontrolled. However, it is difficult to clearly differentiate thermallygrown oxide from other forms of oxide, such as plasma deposited TEOSoxide. One measure of differentiation is the index of refraction.Perfect thermal oxide will have an index of refraction of 1.46. However,process variations do not always permit a perfect thermal oxide to begrown. Therefore, it is recognized that a thermal oxide having an indexof refraction between 1.4 and 1.6 is sufficient for many aspects of thepresent invention.

[0022] In some aspects, the metal foil substrate 102 has a thickness 118in the range of 10 to 500 microns. More preferably, the metal foilsubstrate 102 has a thickness 118 in the range of 50 to 250 microns.Most preferably, the metal foil substrate 102 has a thickness 118 in therange of 100 to 200 microns. A thinner metal foil substrate ispreferable. A thickness of less than 200 microns generally insuresconformability, but a very flexible substrate would have a thickness of150 microns, or less. Reduced weight is another advantage to thinnersubstrates.

[0023] The metal foil substrate surface 104 has an average surfaceroughness (not shown) of less than approximately 200 nanometers (nm).This surface roughness is accomplished by one of two differentprocesses. In the first process, a spin-coat dielectric material 120 isdeposited to overlie the electrical isolation layer 106, having athickness 122 in the range of 200 to 500 nm. In some aspects, thespin-coat dielectric material 120 is a spin-on-glass (SOG) material.Alternately, the surface roughness specification is achieved using achemical-mechanical polishing (CMP) process. When CMP is used, thespin-coat dielectric material 120 need not be used.

[0024] The electrical isolation layer 106 is a material such as SiO2,SiNx, or SiON. The electrical isolation layer 106 has a thickness 124 inthe range of 0.5 to 2 microns. Preferably, the thickness 124 is in therange of 0.5 to 1.5 microns. Most preferably, the thickness 124 is inthe range of 0.5 to 1 microns. Thinner isolation layers increasethroughput and also reducing the stress on the substrate. Typically thestress is balanced with deposition on both sides of the substrate.Hence, it is doubly desirable to reduce the thickness of the electricalisolation layer. However, if the isolation layer is too thin,insufficient isolation is provided, increasing parasitic coupling(parasitic capacitance) between the substrate and the TFT plane 113. Theelectrical isolation layer can also provide, to some extent, protectionagainst the diffusion of impurities from the metal substrate. That is,the electrical isolation layer can act as a diffusion barrier.Therefore, the thickness needs to be optimized from both these points ofusage.

[0025] The polycrystalline silicon 113 has a thickness 126 in the rangeof 25 to 150 nm. Preferably, the polycrystalline silicon 113 has athickness 126 in the range of 25 to 100 nm. Most preferably, thethickness 126 is in the range of 35 to 60 nm.

[0026] The poly-Si thickness drives certain TFT characteristics. Thickerfilms have better microstructure, for example a larger grain size, thattypically provides for higher mobility and ON current. However, thickerfilm TFTs demonstrate higher OFF (leakage) current. Therefore, thinnerfilms are preferable for applications where the OFF current needs to below. Generally, pixel TFTs require a low OFF current. TFTs made fromthermally grown dielectrics can have both advantages. Thermally “grown”SiO2 film consumes part of the poly-Si during its growth. Therefore, onecan start with a thicker poly-Si film, to obtain the advantage ofmicrostructure, and then “thin” it down during the growth of thedielectric to obtain the low leakage current. The SiO2 film typicallyconsumes poly-Si thickness equivalent to ˜54% of the dielectricthickness. In other words, if a 500 Å of thermal SiO2 were grown, 250 Åof poly-Si film would be consumed. Thus, to have 500 Å of poly-Si filmremaining, over 750 Å of poly-Si film would be needed before thermaloxidation. If 1000 Å of thermal SiO2 were grown, the initial poly-Sithickness would have to be even larger (˜1000 Å) to be left with 500 Åof poly-Si film at the end.

[0027] Overall, the gate insulation oxide film 114 has a thickness 128in the range of 10 to 100 nm. In one aspect, the gate insulation film114 is formed exclusively from thermally grown SiO2. However, the gateinsulation film 114 can also be formed in layers to reduce the processtime.

[0028]FIG. 2 is a detailed depiction of the gate insulation oxide film114 of FIG. 1. Gate insulation oxide film 114 includes a first oxidefilm layer 200 having an index of refraction in the range of 1.4 to 1.6.The first oxide film layer 200 is thermally grown. The gate insulationoxide film 114 further includes a second oxide film layer 202 overlyingthe first oxide layer 200 having an index of refraction in the range of1.4 to 2.0. In some aspects, the second oxide film 202 is formed byplasma deposition.

[0029] The first oxide film layer 200 has a thickness 204 in the rangeof 20 to 30 nm. The second oxide film layer 202 has a thickness 206 inthe range of 40 to 100 nm. Preferably, the second oxide film layer 202has a thickness 206 in the range of 50 to 70 nm. Typically, both thefirst 200 and second 202 oxide film layers are a SiO2 material.

Functional Description

[0030] The present invention TFT combines the use of high temperaturethermal oxidation with solid-phase-crystallized poly-Si material.Thermal oxidation requires temperatures in the range of 900-1150° C.,that are not compatible with traditional flexible substrates. However,this problem is solved in the present invention by utilizing flexiblethin metal foils.

[0031] The combination of thermal oxidation with SPC has two distinctbenefits:

[0032] 1) a gate insulator film of excellent bulk and interface qualitycan be formed; and,

[0033] 2) the quality of the poly-Si film itself, is improved byeffectively annealing out defects in the poly-Si grains.

[0034] As a result of these benefits, the devices made with the presentinvention process combine the feature of very high mobility, with a lowthreshold voltage and very steep subthreshold swing. When the metal foilitself is sufficiently thin, less than 200 μm, it can be bent or rolledeasily. Systems fabricated on such thin foils are robust and yet“flexible” as defined above. In this context, a flexible microsystem canconsist of a display only, a display with driving electronics, a displaywith driving electronics and sensing electronics, or a non-displaysystem, such as a sensor array or a flexible storage (memory)microsystem that can be a stand-alone unit, or one that has the abilityto attach to another system for input/output operations.

[0035] One aspect of the invention is the combination of a thin metalfoil substrate, such as 304 SS, Kovar alloy, Inconel alloy, Ti, orequivalent metals, with the solid-phase crystallization of Si film,having a thickness of 500-1500 Å, in the range of 600-900° C. One otheraspect of the process sequence includes a planarization step performedon the as-received metal foil substrate, prior to metal deposition. Thisprocess is important if the surface roughness of the as-formed metalfoil is significant enough to cause yield loss.

[0036] A thermal oxidation follows with a temperature in the range of950-1200° C., to thermally grow a SiO2 gate insulator film withthickness in the range of 100-1000 Å. A variation to the processsequence involves thermal growth of a thin gate insulator layer, forexample 200-300 Å, followed by deposition of SiO2 gate insulator by adifferent method, for example, plasma-enhanced chemical vapor deposition(PECVD) up to a total, combined thickness of approximately 1000 Å. Thisvariation expedites process throughput in some circumstances.

[0037]FIG. 3 is a flowchart illustrating the present invention methodfor forming a thin-film transistor (TFT) on a flexible substrate.Although this method is depicted as a sequence of numbered steps forclarity, no order should be inferred from the numbering unlessexplicitly stated. It should be understood that some of these steps maybe skipped, performed in parallel, or performed without the requirementof maintaining a strict order of sequence. The methods start at Step300. Step 302 supplies a metal foil substrate with a surface. Step 304planarizes the metal foil substrate surface. Step 306 deposits anelectrical isolation layer overlying the planarized metal foil substratesurface. Step 308 deposits amorphous silicon overlying the electricalinsulation layer. Step 310 anneals the amorphous silicon to formpolycrystalline silicon. Step 312 thermally grows a gate insulation filmoverlying the polycrystalline film. Step 314 forms transistor gate,source, and drain regions.

[0038] In some aspects of the method, annealing the amorphous silicon toform polycrystalline silicon in Step 310 includes annealing at atemperature greater than 700 degrees C. In some aspects, Step 310includes using a solid-phase crystallization (SPC) annealing process.Using a SPC annealing process in the annealing Step 310 includes using aprocess such as furnace or rapid-thermal annealing (RTA). Then, Step 310includes annealing at a temperature in the range of 700 to 1000 degreesC. for a period of time in the range of 2 seconds to 30 minutes.Preferably, Step 310 includes annealing at a temperature in the range of750 to 950 degrees C. for a period of time in the range of 2 seconds to30 minutes.

[0039] Alternately in other aspects, annealing the amorphous silicon toform polycrystalline silicon in Step 310 includes using a Laser-InducedLateral Growth (LILaC) annealing process. While either annealing processcan be used, the SPC annealing is more likely to expedite the process.

[0040] LILAC relies on lateral growth of Si grains using very narrowlaser beams, that are generated by passing a laser beam through abeam-shaping mask, and projecting the image of the mask to the film thatis being annealed. The initially amorphous silicon film is irradiated bya very narrow laser beamlet, with typical widths of a few microns (i.e.3-5 μm). Such small beamlets are formed by passing the original laserbeam through a mask that has open spaces or apertures, and projectingthe beamlets onto the surface of the annealed Si-film. A step-and-repeatapproach is used. The shaped laser “beamlet” irradiates the film andthen steps by a distance smaller than half of the width of the slit. Asa result of this deliberate advancement of each beamlet, grains areallowed to grow laterally from the crystal seeds of the poly-Si materialformed in the previous step. This is equivalent to laterally “pulling”the crystals, as in zone-melting-crystallization (ZMR) method or othersimilar processes. As a result, the crystal tends to attain very highquality along the “pulling” direction, in the direction of the advancingbeamlets. This process occurs simultaneously at each slit on the mask,allowing for rapid crystallization of the area covered by the projectionof the mask on the substrate. Once this area is crystallized, thesubstrate moves to a new (unannealed) location and the process isrepeated.

[0041] In some aspects a further step, Step 311 patterns the silicon toform silicon islands after the annealing process in Step 310. Thermallygrowing a gate insulation film in Step 312 includes thermally growing agate insulation layer overlying polycrystalline islands. Alternately,patterning the silicon to form silicon islands in Step 311 occurs priorto annealing of the amorphous silicon in Step 310.

[0042] In some aspects, supplying a metal foil substrate with a surfacein Step 302 includes supplying a metal foil material such as Ti, Inconelalloy, stainless steel, or Kovar. Step 302 includes supplying a metalfoil having a thickness in the range of 10 to 500 microns. Preferably,Step 302 supplies a metal foil having a thickness in the range of 50 to250 microns. Most preferably, the metal foil has a thickness in therange of 100 to 200 microns.

[0043] In some aspects, planarizing the metal foil substrate surface inStep 304 includes chemical-mechanical polishing (CMP) the metal foilsubstrate surface. Then, Step 304 includes polishing to an averagesurface roughness of less than approximately 200 nanometers (nm).Alternately, planarizing the metal foil substrate surface in Step 304includes spin-coating a dielectric material overlying the metal foilsubstrate surface. In some aspects, spin-coating a dielectric materialoverlying the metal foil substrate surface includes forming a dielectriclayer having a thickness in the range of 200 to 500 nm. In otheraspects, spin-coating a dielectric material overlying the metal foilsubstrate surface includes forming a dielectric layer from aspin-on-glass (SOG) material.

[0044] In some aspects of the method, depositing an electrical isolationlayer overlying the planarized metal foil substrate surface in Step 306includes depositing an electrical isolation layer using a material suchas SiO2, SiNx, or SiON. In other aspects, the electrical isolation layeris deposited to a thickness in the range of 0.5 to 2 microns.Preferably, the thickness is in the range of 0.5 to 1.5 microns. Mostpreferably, the thickness is in the range of 0.5 to 1 microns.

[0045] In some aspects, depositing amorphous silicon in Step 308includes depositing amorphous silicon having a thickness in the range of25 to 150 nm. Preferably, Step 308 includes depositing amorphous siliconhaving a thickness in the range of 25 to 100 nm. Most preferably, Step308 includes depositing amorphous silicon having a thickness in therange of 35 to 60 nm.

[0046] In some aspects a further step, Step 309, following thedeposition of the amorphous silicon in Step 308, p-dopes the amorphoussilicon to adjust the threshold voltage.

[0047] In some aspects, thermally growing a gate insulation film in Step312 includes substeps. Step 312 a forms a first film polycrystallinesilicon layer. Step 312 b thermally oxidizes the first film layer. Inother aspects, thermally oxidizing the first film layer in Step 312 bincludes annealing at temperature in the range of 900 to 1150 degrees C.for a period of time in the range of 2 to 60 minutes. In some aspects,forming a first film polycrystalline silicon layer in Step 312 aincludes forming a first film layer having a thickness in the range of10 to 100 nanometers (nm).

[0048] Alternately, thermally growing a gate insulation film in Step 312includes an additional substep, Step 312 c, of plasma depositing asecond layer of oxide overlying the first film. Then, forming a firstfilm layer in Step 312 a includes depositing a first film layer having athickness in the range of 10 to 50 nm. Preferably, the first film layerhas a thickness in the range of 20 to 30 nm. Plasma depositing a secondlayer of oxide overlying the first film in Step 312 c then includesdepositing a layer having a thickness in the range of 40 to 100 nm.Preferably, the second layer of oxide has a thickness in the range of 50to 70 nm. In some aspects, plasma depositing a second layer of oxideoverlying the first film in Step 312 c includes depositing a TEOS-SiO2material.

[0049] A TFT formed on metal foil substrate, with a SPC polysiliconlayer, and a thermally oxidized gate insulation layer has been provided.A process to fabricate the above-mention TFT has also been provided.Examples have been provided of some material thicknesses and processtemperatures, but the present invention is not necessarily limited tojust these examples. Other variations and embodiments of the inventionwill occur to those skilled in the art.

We claim:
 1. A method for forming a thin-film transistor (TFT) on aflexible substrate, the method comprising: supplying a metal foilsubstrate with a surface; depositing amorphous silicon; annealing theamorphous silicon to form polycrystalline silicon; and, thermallygrowing a gate insulation film overlying the polycrystalline film. 2.The method of claim 1 wherein annealing the amorphous silicon to formpolycrystalline silicon includes annealing at a temperature greater than700 degrees C.
 3. The method of claim 2 wherein annealing the amorphoussilicon to form polycrystalline silicon includes using a solid-phasecrystallization (SPC) annealing process.
 4. The method of claim 1wherein annealing the amorphous silicon to form polycrystalline siliconincludes using a Laser-Induced Lateral Growth (LILaC) annealing process.5. The method of claim 1 further comprising: planarizing the metal foilsubstrate surface; depositing an electrical isolation layer overlyingthe planarized metal foil substrate surface; and, wherein depositingamorphous silicon includes depositing amorphous film overlying theelectrical insulation layer.
 6. The method of claim 5 furthercomprising: patterning the silicon to form silicon islands; and, whereinthermally growing a gate insulation film includes thermally growing agate insulation layer overlying polycrystalline islands.
 7. The methodof claim 6 further comprising: forming transistor gate, source, anddrain regions.
 8. The method of claim 1 wherein supplying a metal foilsubstrate with a surface includes supplying a metal foil materialselected from the group including titanium (Ti), Inconel alloy,stainless steel, and Kovar.
 9. The method of claim 8 wherein supplying ametal foil substrate with a surface includes supplying a metal foilhaving a thickness in the range of 10 to 500 microns.
 10. The method ofclaim 9 wherein supplying a metal foil substrate with a surface includessupplying a metal foil having a thickness in the range of 50 to 250microns.
 11. The method of claim 10 wherein supplying a metal foilsubstrate with a surface includes supplying a metal foil having athickness in the range of 100 to 200 microns.
 12. The method of claim 5wherein planarizing the metal foil substrate surface includeschemical-mechanical polishing (CMP) the metal foil substrate surface.13. The method of claim 12 wherein chemical-mechanically polishing themetal foil substrate surface includes polishing to an average surfaceroughness of less than approximately 200 nanometers (nm).
 14. The methodof claim 5 wherein planarizing the metal foil substrate surface includesspin-coating a dielectric material overlying the metal foil substratesurface.
 15. The method of claim 14 wherein spin-coating a dielectricmaterial overlying the metal foil substrate surface includes forming adielectric layer having a thickness in the range of 200 to 500 nm. 16.The method of claim 14 wherein spin-coating a dielectric materialoverlying the metal foil substrate surface includes forming a dielectriclayer from a spin-on-glass (SOG) material.
 17. The method of claim 5wherein depositing an electrical isolation layer overlying theplanarized metal foil substrate surface includes depositing anelectrical isolation layer from a material selected from the groupincluding SiO2, SiNx, and SiON.
 18. The method of claim 17 whereindepositing an electrical isolation layer overlying the planarized metalfoil substrate surface includes depositing a layer having a thickness inthe range of 0.5 to 2 microns.
 19. The method of claim 18 whereindepositing an electrical isolation layer overlying the planarized metalfoil substrate surface includes depositing a layer having a thickness inthe range of 0.5 to 1.5 microns.
 20. The method of claim 19 whereindepositing an electrical isolation layer overlying the planarized metalfoil substrate surface includes depositing a layer having a thickness inthe range of 0.5 to 1 microns.
 21. The method of claim furthercomprising: following the deposition of the amorphous silicon, p-dopingthe amorphous silicon to adjust the threshold voltage.
 22. The method ofclaim 3 wherein using a SPC annealing process includes using a processselected from the group including furnace and rapid-thermal annealing(RTA).
 23. The method of claim 22 wherein annealing the amorphoussilicon at a temperature greater than 700 degrees C. includes annealingat a temperature in the range of 700 to 1000 degrees C. for a period oftime in the range of 2 seconds to 30 minutes.
 24. The method of claim 23wherein annealing the amorphous silicon at a temperature greater than700 degrees C. includes annealing at a temperature in the range of 750to 950 degrees C. for a period of time in the range of 2 seconds to 30minutes.
 25. The method of claim 1 wherein thermally growing a gateinsulation film includes: forming a first film polycrystalline siliconlayer; and, thermally oxidizing the first film layer.
 26. The method ofclaim 25 wherein thermally oxidizing the first film layer includesannealing at temperature in the range of 900 to 1.150 degrees C. for aperiod of time in the range of 2 to 60 minutes.
 27. The method of claim26 wherein forming a first film polycrystalline silicon layer includesforming a first film layer having a thickness in the range of 10 to 100nanometers (nm).
 28. The method of claim 25 wherein thermally growing agate insulation film further includes plasma depositing a second layerof oxide overlying the first film.
 29. The method of claim 28 whereinforming a first film layer includes depositing a first film layer havinga thickness in the range of 10 to 50 nm.
 30. The method of claim 29wherein depositing a first film layer includes depositing a layer havinga thickness in the range of 20 to 30 nm.
 31. The method of claim 29wherein plasma depositing a second layer of oxide overlying the firstfilm includes depositing a layer having a thickness in the range of 40to 100 nm.
 32. The method of claim 31 wherein plasma depositing a secondlayer of oxide overlying the first film includes depositing a layerhaving a thickness in the range of 50 to 70 nm.
 33. The method of claim28 wherein plasma depositing a second layer of oxide overlying the firstfilm includes depositing a TEOS-SiO2 material.
 34. The method of claim 6wherein patterning the silicon to form silicon islands includespatterning polycrystalline islands following the annealing of theamorphous silicon.
 35. The method of claim 6 wherein patterning thesilicon to form silicon islands includes patterning amorphous siliconislands prior to annealing of the amorphous silicon.
 36. The method ofclaim 1 wherein depositing amorphous silicon includes depositingamorphous silicon having a thickness in the range of 25 to 150 nm. 37.The method of claim 36 wherein depositing amorphous silicon includesdepositing amorphous silicon having a thickness in the range of 25 to100 nm.
 38. The method of claim 37 wherein depositing amorphous siliconincludes depositing amorphous silicon having a thickness in the range of35 to 60 nm.
 39. A method for forming a thin-film transistor (TFT) on aflexible substrate, the method comprising: supplying a metal foilsubstrate with a surface; planarizing the metal foil substrate surface;depositing an electrical isolation layer overlying the planarized metalfoil substrate surface; depositing amorphous silicon overlying theelectrical isolation layer; annealing the amorphous silicon at atemperature greater than 700 degrees C. to form polycrystalline silicon;and, thermally growing a gate insulation film.
 40. A thin-filmtransistor (TFT) on a flexible substrate comprising: a metal foilsubstrate with a surface; an electrical isolation layer overlying themetal foil substrate surface; drain, source, and channel regions formedfrom polycrystalline silicon overlying the electrical isolation layer; agate insulation oxide film overlying the polycrystalline silicon havingan index of refraction in the range of 1.4 to 1.6; and, a gate overlyingthe gate insulation oxide layer.
 41. The TFT of claim 40 wherein themetal foil substrate has a thickness in the range of 10 to 500 microns.42. The TFT of claim 41 wherein the metal foil substrate has a thicknessin the range of 50 to 250 microns.
 43. The TFT of claim 42 wherein themetal foil substrate has a thickness in the range of 100 to 200 microns.44. The TFT of claim 40 wherein the metal foil substrate surface has anaverage surface roughness of less than approximately 200 nanometers(nm).
 45. The TFT of claim 40 further comprising: a spin-coat dielectricmaterial overlying the metal foil substrate having a thickness in therange of 200 to 500 nm.
 46. The TFT of claim 45 wherein the spin-coatdielectric material is a spin-on-glass (SOG) material.
 47. The TFT ofclaim 40 wherein the electrical isolation layer is a material selectedfrom the group including SiO2, SiNx, and SiON.
 48. The TFT of claim 47wherein the electrical isolation layer has a thickness in the range of0.5 to 2 microns.
 49. The TFT of claim 48 wherein the electricalisolation layer has a thickness in the range of 0.5 to 1.5 microns. 50.The TFT of claim 49 wherein the electrical isolation layer has athickness in the range of 0.5 to 1 microns.
 51. The TFT of claim 40wherein the polycrystalline silicon has a thickness in the range of 25to 150 nm.
 52. The TFT of claim 51 wherein the polycrystalline siliconhas a thickness in the range of 25 to 100 nm.
 53. The TFT of claim 52wherein the polycrystalline silicon has a thickness in the range of 35to 60 nm.
 54. The TFT of claim 40 wherein the gate insulation oxide filmhas a thickness in the range of 10 to 100 nm.
 55. The TFT of claim 54wherein the gate insulation oxide film includes: a first oxide filmlayer having an index of refraction in the range of 1.4 to 1.6; and, asecond oxide film layer overlying the first oxide layer having an indexof refraction in the range of 1.4 to 2.0.
 56. The TFT of claim 55wherein the first oxide film layer has a thickness in the range of 20 to30 nm.
 57. The TFT of claim 55 wherein the second oxide film layer has athickness in the range of 40 to 100 nm.
 58. The TFT of claim 57 whereinthe second oxide film layer has a thickness in the range of 50 to 70 nm.59. The TFT of claim 55 wherein the second oxide film layer is a SiO2material.
 60. The TFT of claim 55 wherein the first oxide film layer isa SiO2 material.
 61. The TFT of claim 40 wherein the metal foilsubstrate is a material selected from the group including titanium (Ti),Inconel alloy, stainless steel, and Kovar.